This position is responsible for Graphics Hardware Validation and Debug related activities covering the various Features of Processor Graphics like 3D, GTI, blitter, and GPGPU, Media, Display for post-silicon validation and debug. From a technical debug perspective, drive a regular debug forum for the team to help expedite debugs and make sure the appropriate external stakeholders are engaged, and when appropriate, form task force sessions to drive more urgent issues to resolution. This position will leverage best known methods and tools from existing Intel validation organizations.
Responsibilities will include but not be limited to:
- Develop post-si validation test strategies, plans, and schedules,
- Drive Execution of the written test plans and procedures
- Plan scheduling of weekly tasks for meeting medium and long-term validation deliverables
- Monitor progress against schedule communicating status
- Identify and collect pertinent data to influence decisions when presenting to various management forums
- Drive issue resolution with software and hardware development teams
- Enhancing existing pre/post-si validation methodology and processes
- BS in Electrical Engineering, Computer Engineering or Computer Science or related field.
- 6+ years of experience with Post Silicon Debug /Validation and/or Emulation (4+ years of experience with a Masters Degree or 2+ years with a PhD)
- 6+ years of semiconductor industry/high technology based experience Graphics knowledge / HW validation background
- Knowledge of Windows/MacOS driver environment.
- Device Driver and Kernel level debugging knowledge
- RTL debug knowledge
- Demonstrated excellent problem solving skills
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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